# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s
---
name:            fold_ror_eor
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
liveins:
  - { reg: '$w0' }
body:             |
  bb.1.entry:
    liveins: $w0

    ; Our codegen differs from SDAG here, we decide to fold in LHS
    ; operand instead of RHS since they're both rotates and XOR is commutative.
    ; Either is valid.

    ; CHECK-LABEL: name: fold_ror_eor
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[EXTRWrri:%[0-9]+]]:gpr32 = EXTRWrri [[COPY]], [[COPY]], 11
    ; CHECK: [[EORWrs:%[0-9]+]]:gpr32 = EORWrs [[EXTRWrri]], [[COPY]], 198
    ; CHECK: $w0 = COPY [[EORWrs]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %13:gpr(s64) = G_CONSTANT i64 6
    %2:gpr(s32) = G_ROTR %0, %13(s64)
    %14:gpr(s64) = G_CONSTANT i64 11
    %4:gpr(s32) = G_ROTR %0, %14(s64)
    %5:gpr(s32) = G_XOR %2, %4
    $w0 = COPY %5(s32)
    RET_ReallyLR implicit $w0

...
---
name:            fold_ror_eor_rhs_only
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
liveins:
  - { reg: '$w0' }
  - { reg: '$w1' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.1.entry:
    liveins: $w0, $w1

    ; CHECK-LABEL: name: fold_ror_eor_rhs_only
    ; CHECK: liveins: $w0, $w1
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
    ; CHECK: [[EORWrs:%[0-9]+]]:gpr32 = EORWrs [[COPY1]], [[COPY]], 198
    ; CHECK: $w0 = COPY [[EORWrs]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = COPY $w1
    %9:gpr(s64) = G_CONSTANT i64 6
    %3:gpr(s32) = G_ROTR %0, %9(s64)
    %4:gpr(s32) = G_XOR %1, %3
    $w0 = COPY %4(s32)
    RET_ReallyLR implicit $w0

...
